Optical communication systems are known in which optical signals carrying data are transmitted from a first node to a second or receive node over an optical fiber. At the receive node, the optical signals are converted into corresponding electrical signals, which are then further processed.
Various techniques are known for detecting or sensing the data carried by an optical signal. In one such technique, known as “coherent detection” a light source or laser, also referred to as a local oscillator, is provided at the receive node. Incoming light of the received optical signal is split by a polarization beam splitter into two orthogonal signals. Each signal combined with the light output from the local oscillator is passed through a 90-deg hybrid with four or four pairs of photodiodes detect the outputs of the two hybrids to generate the corresponding electrical signals.
A coherent detection-based receiver or coherent receiver typically includes four analog-to-digital converters (ADC). The electrical signals output from the photodiodes are typically analog signals, which are sampled at a rate greater than or equal to the symbol (baud) rate by the ADC. Theoretically, according to the Nyquist Theorem, the sampling rate can be as low as one sample per symbol, and systems have been proposed in which the sampling rate is less than or equal to twice the baud rate.
As data or baud rates increase, the ADC preferably has to have a sufficient sampling rate to accommodate such increased data rates. It is envisioned that higher overhead forward error correction (FEC) may be utilized in the future to enable further transmission distance, further increasing the required sampling rate and complexity of the ADC.
The coherent receiver in the receive node typically also includes a digital signal processor (DSP) core which receives digital signal data from the ADCs. The complexity of the design of the DSP is based at least on the sampling rate of the received digital signal data. For example, a DSP core that processes one sample per symbol is one half the complexity of a DSP core that processes two samples per symbol. Determination of the optimal sampling rate for the DSP must also take into consideration particular constraints such as power, timing, etc.
In contrast, determination of the optimum sampling rate for the ADC may take into consideration other constraints including analog bandwidth, noise, and jitter. Another constraint is the effective number of bits (ENOB) in the digitized signal, i.e., the amount of noise introduced by the A/D converter.
It is desirable that both the ADC and the DSP core circuits be optimized independently of each other. For example, the ADC may be optimized to sample at a given rate to satisfy a given set of constraints, while the DSP core may be optimized to sample at a different rate to satisfy a different set of constraints. As an example, it may be desirable for the ADC to sample at 1.8 times the baud rate in order to reduce aliasing noise, whereas a different sampling rate of 1.5 times the baud rate may be desirable for the DSP core in order to realize reduced circuit complexity and heat dissipation. One difficulty in accommodating multiple data rates in the coherent receiver is that the ADC and the associated ADC clock structure are typically tuned for performance and thus have very narrow tuning ranges. For example, an ADC designed for 23 Gigasamples per second (GS/s) typically provides only a few percent tuning range at the sampling rate. As a result, it may difficult to implement a design for a coherent receiver that accommodates this ADC requirement while also accommodating two data rates that differ by 25%, for example 40 Gb/s and 50 Gb/s.
In addition, a DSP core needed for a particular application may be designed to operate at rates that are not synchronous with the baud rate. As a result, the required ADC sampling rate can be different than the DSP sampling rate, and thus making the ADC incompatible with the DSP. It is desirable to have an apparatus, method, and system for implementation of multiple data rates for the coherent receiver circuitry, such that the ADC operates at a sampling rate that is independent of the sampling rate of the DSP to enable operation at higher baud rates and with higher FEC overhead.